1. Field of the Invention
The present invention relates to a data processing apparatus and method for accessing a memory having a plurality of memory locations for storing data values, and in particular to such a data processing apparatus and method that protects memory accesses. The term `data value` is used herein to refer to both instructions and to items or blocks of data, such as data words.
2. Description of the Prior Art
It is known to segment memory into a number of separate logical regions, and to specify protection attributes for each of the regions, such as whether the regions are accessible in supervisor mode only, whether the regions are cacheable, bufferable in a cache based system, etc, to control access to those memory regions. Hence, if a processor issues a memory address which falls within a particular memory region, then the protection attributes for that region can be used to determine whether the processor, in its current mode of operation, is entitled to access that memory address, and to determine whether data values retrieved from that memory region are cacheable, whether data values to be written to that memory region are bufferable, etc. Often, but not exclusively, such protection mechanisms are used in virtual memory systems in association with virtual to physical address translation.
In most implementations, there is limited flexibility provided for defining the logical regions. The logical regions may typically be of a fixed size, such as 4 kb regions, although some techniques may improve flexibility somewhat by providing a few different sized regions, such as 1 kb, 2 kb and 4 kb regions. Typically, if different sized regions are provided, they will be constrained to vary by powers of two, since the hardware necessary to compare addresses to determine the logical regions containing those addresses can be less complex if the regions are constrained to sizes that vary by power of two.
Using the above approach, it is possible to specify user areas of memory, and supervisor areas of memory. For example, consider the case where fixed size logical regions of 4 kb are provided, and the system requires 4 kb of supervisor code and 12 kb of user code, both of which must be mapped into a 16 kb RAM. Four logical regions need to be defined to achieve this, ie. one 4 kb region for the supervisor code, and three 4 kb regions for the user code.
It would be desirable to provide the above functionality whilst defining less regions than are required in the above-described prior art techniques, thereby improving the flexibility of the system.